Nirmal Pratheep Natarajan

Right now

Agentic AI, recursive self-improvement (RSI), reinforcement learning, and ML for design automation.

Work

• 2012 – now

  AMD (formerly Xilinx), San Jose. Senior Staff / Research Engineer, AI/ML & Design Automation.

  • Built self-improving agent loops that cut runtime and memory use in a production codebase by 20 to 30%, with no manual intervention.
  • Built agents that debug chip simulations and doubled the regression pass rate and device maturity.
  • Trained an RL agent that beat default heuristics by 2% on Vivado placement QoR, and built ML delay prediction that cut turnaround from several days to hours.
  • Lead a team of 10+ engineers across global sites, building tools that generate chip data for 10nm, 7nm and 2nm FPGA nodes.
• 2010 – 2011

  Wipro, Chennai. Consultant. Payroll automation on Oracle PeopleSoft 9.0, working with product managers and customers on rules, bug fixes and upgrades.

• 2007 – 2010

  Cognizant, Chennai. Technical Analyst. Performance review automation on Oracle PeopleSoft 8, with the same mix of rules, bug fixes and upgrades.

Selected work

At AMD

• AutoTune (RSI). An actor/critic loop that tunes a target function or flow inside guardrails and an automated test suite. A frontier model proposes and reviews changes while a medium model monitors and profiles.
• Simulation-debugging agents (RSI). Single and multi-agent systems that find why regressions fail. A step-by-step flow from behavioral models to full-chip simulation prunes what doesn't matter, and a job-scheduler step finds the smallest set of fixes that makes a simulation pass. It repeats until the simulation passes and records every issue along the way.
• Floorplan generation (RSI). Turns hardware floorplans into software ones with stacking, packing, expanding and shrinking moves, trying combinations of fixes until the result passes checks like clock routing and configuration.
• RL for Vivado placement. I generated offline data for many placement-directive combinations and built a simulator that returns rewards from it. A PPO policy learns to pick directives based on timing, congestion, area and routing quality, using GIN features on netlists with up to 15M nodes. It beat default heuristics by 2% on placement QoR, and more designs that used to fail timing now pass. Training runs on Ray with population-based training, and inference takes under a second.
• Flow-triage agents. An agentic framework that triages issues, corrects itself and evaluates in Docker. It reverse-engineers past issues into reusable skills using augmented data and generated unit tests.
• ML delay prediction. Predicts delay from design complexity (LUT/register pressure, congestion, pin density), with automated fine-tuning, monitoring and drift detection.
• Infrastructure. A client/server system (Boost Asio + Protobuf) with 3x throughput, parallel processing that gave 20x scale for chiplet devices, a graph compression pipeline that turns 1B paths into 500K patterns, and a compiler-like tool that parses SQL and generates opcodes to run on FPGA (published on the Amazon AWS Marketplace).

On my own time

• Agentic kernel optimizer. Two agents in a loop: one builds, runs and evaluates MoE kernels on B200, and the other profiles with Nsight until they hit the SPOL limit. About 20% faster than naive PyTorch.
• Auto-research DAG scheduler. Scheduling for large computational DAGs on memory-constrained accelerators. It finds DAG motifs and builds strategies from greedy and heuristic algorithms, with a multi-armed bandit learning which heuristic suits each motif. 50% lower latency than baseline schedulers.
• Reasoning with GRPO. Baseline, then SFT, then GRPO on Qwen 2.5 Math 1.5B, for a 14.2× accuracy gain. Training runs.
• Car agent. Learned to finish every track with curriculum training and PPO. Training run.
• Small-model pre-training. A 1B seed model with a 33% throughput gain from custom Triton kernels and fused Flash Attention, plus SmolLM v2 on FineWeb-Edu.
• ImageNet classifier. ResNet-50 at 77.4% Top-1. I've also built a Tamil BPE tokenizer and an MNIST architecture search.

Papers & contests

• 2026
  Ranked 10th in the agentic track at MLSys 2026, with the agentic kernel optimizer above.
• AMD
  Deep RL for FloorPlan Optimization. Internal conference finalist; arXiv coming. FPGA floorplan optimization framed as RL, with GIN on 15M-node netlists and a 2% placement QoR gain over default heuristics.
• AMD
  ML-based Delay Prediction. Internal conference finalist.
• 2009
  Adaptive Pilot Utilization for OFDM Channel Estimation in a Time Varying Channel. With Jungsub B., at the IEEE Wireless and Microwave Technology Conference (WAMICON), Florida.
• 2007
  Top 15 finalist, Innovate India Design Contest (ALTERA).

Say hi

I'm happy to talk about agents, RL, chip design or mentoring. The easiest way to reach me is nirmalpratheep@gmail.com, or find me on LinkedIn and GitHub.